August 14th, 2020 Progress Report

Overlay Device Generation

    Overlay generation was merged this week.  Remaining work will focus on making it easier to use and providing detailed documentation.

 Testing

    Working towards a set of more advanced tests for partition region and overlay architectures.  Specifically I'm going to be using the zynq 7020 architecture and a DMA controller connected to the PS to interface with partition regions.  This way I'll be able to have a streaming interface in and out of each partition region that can then have different logic mapped to change the results the PS receives.

    For example, the partition region could contain an identity module, an add 1 module, or a rendering module, each of which can take the same inputs but produce different outputs.  These modules can then be changed without having to recompile the overlay.

    The only concern I have that I'm stilling trying to figure out is license issues.  I can finish removing all xilinx IP for the most part, but there is still an issue of the wrapper for the PS7 being written by Xilinx (although I can probably write my own).  There is also an issue of the licensing for verilog generated by Vivado HLS.  The solution here might be to write some simple modules by hand at first or to look into an alternative HLS.

 Last Week

    This upcoming week is the last week of summer of code.  I will be finishing up documentation and general code clean up before the week is over.  Hopefully these more advanced test cases will be able to be included as well.

    I will likely continue to contribute to SymbiFlow in the future as it is very relevant to my research interests, but the frequency will definitely slow down after going back to school.