August 7th, 2020 Progress Report

Overlay Device Generation

    Overlay generation CI is now green and just needs some final cleanup before being merged.  I will then be working on documentation to ensure others are able to use my work.

 Partition Regions with >1 Clock Region

    To support large enough partition regions to be useful in many cases, they must be able to span across multiple clock regions.  This produces a number of complications.  Most importantly, clocks can't cross over clock region boundaries horizontally on their own.  To remedy this issue we must either artificially connect together where the clock enters the partition region for each clock region (aka the output nodes of the BUFH) or expose the entire global clock tree for a clock that enters the partition region.

    Currently I am exposing the global clock tree by creating a synth tile at the output of a BUFG.  This seems to be working but will potentially create some issues in the future with sharing BUFGs between multiple partition regions.

    The other issue I have been having with these large partition regions is with the constant networks.  It seems that constant networks are not able to be routed over clock region boundaries, but this should be able to remedied by exposing more of the constant network as it is artificial anyways.

    My test case for these larger partition regions is the rendering PRFlow benchmark on the 7020, which requires a large partition region for a monolithic design.