July 31st, 2020 Progess Report

Overlay Device Generation

    I made a few final fixes to the overlay architecture generation, which should now be very close to being merged.  An overlay and multiple partition regions can be defined and mapped to separately and then have the resulting fasm merged automatically merged by cmake before generating a bitstream.  CI is red right now because of a regression in fasm2bels, but that should be fixed soon.

 PRFlow Rendering Benchmark with SymbiFlow Partition Regions

    One of the important test cases I would like to use is the PRFlow implementation of the Rosetta rendering benchmark.  I have this test working in SymbiFlow on the 7020 with no partition regions, so the next step is to define a partition region to separate the user rendering application from the axi dma logic.

    I still do not have a good algorithm for automatically picking partition pins, so for now I will have to either manually pick them or write some simplistic algorithm.

    One major problem I have run into and am trying to address currently having a partition region that spans multiple clock regions.  The clock has to be fed into each clock region, which is easy enough using synth tiles, but I still need some method for letting the user logic know the two synth IOs are actually the same clock.  Otherwise, the user will have to manually partition the logic between the two clock regions.

True Partial Reconfiguration

   I have also started looking at live partial reconfiguration.  I think the majority of this work would be getting a correct header for the frames being sent, but I still need to look into this more.  I will try asking others for help soon.