July 21st, 2020

• Realized I made a mistake in the 2 clock overlay generation
• Caused the second clock to not get generated
• Changed overlay to use PLL properly
• 2 clocks are properly being fed into the partition region now
• Can be seen in the following video. The top row is a 4 bit counter running off a 100 MHz clock and the bottom row is a 4 bit counter running off a 50 MHz clock generated outside the partition region
• Video:

• Started working on supporting brams with shared read/write ports
• Required for Rosetta rendering benchmark