July 17th, 2020 Progress Report

Overlay Device Generation

    The big news of this week is that overlay generation with a single partition region works on hardware! I am still using the required fasm features in the design.json definition to merge the overlay and partition region fasm, but it should also be possible to just merge the end fasm together (this will be required for multiple partition region overlays).

Overlay Tests

    The main test I have been running is the simplest one I could imagine to show the overlay generation working on hardware. The overlay maps the switches and LEDs into the partition region, and the partition region connects these together.  There are two versions, one that connects them directly, and one that reverses which switch connects to which LED.

    First thing next week will be adding more tests, especially testing more complex logic inside the partition region.  I also want to try adding another partition region and move around the first one to make sure the overlay generation works in a more general case.

Overlay Device Generation Issues

   Getting overlay device generation working on hardware caused me to run into a number of issues I had not considered before.

    The biggest lesson was being required to add syn-ibufs and syn-obufs to the architecture to force synthetic IOs to get packed into synth IO tiles instead of real IOs. This work consumed a lot of time this week, but in the end is a fairly good solution. Only issue currently is that syn-ibufs and syn-obufs must be manually inserted in the verilog, but Keith thinks this could be resolved by having yosys automatically add them.

    The other issue that took a while to fix this week was constant net routing, where VPR was unable to route constant nets at all.  Turns out this was a silly mistake in my overlay architecture generation that didn't have routing_import place a synthetic edge for VCC and GND.

    Overall, this was a very productive week and I should hopefully be mostly out of the weeds of fiddling with architecture and rr_graph generation.