July 15th, 2020

• Synth tile from node was merged into arch defs master
• Finished writing test cases for overlay.py and got those changes merged into prjxray
• Realized there was an issue with overlay io constraints
• VPR packed synth IOs into real IOPADs in the netlist, making placement on synth IOs impossible
• Solution is to add a SYN_OBUF and SYN_IBUF pb type to the architecture, allowing VPR to distinguish between real and synth IOs
• Currently these SYN_OBUFs and SYN_IBUFs have to be added explicitly in verilog, but I should be able to add a pass to yosys to add them automatically