June 26th, 2020 Progress Report

Zynq 7020

 

    This week I have made a lot of progress on a mix of items.  I added final touches to zynq 7020 support, including CI and fixing the pynq z1 counter test to include an explicit BUFG.  These changes were merged into master earlier this week, but there is still a bit more work to test the 7020 support for other boards so they can be supported as well.

Map to VPR Coord Fix

    Much of this week was also spent on diagnosing and creating a proper fix for some synth tile locations mapping to multiple logical tiles. #1549 should be merged soon to fix this issue and allow synth tiles to be placed at arbitrary locations.  This fix, along with the ability to create synth IOs from node names, will go a long way in making the ROI a more general partition region that can be easily defined.

Heterogeneous Synth IO Tiles

 

    I am close to having heterogeneous synth IO tiles supported in symbiflow.  These use the heterogeneous tiles feature of VPR upstream, combined with increased capacity, to allow an arbitrary number of SYN-INPADs and SYN-OUTPADs to be placed at the same VPR coordinate.  This feature will allow denser partition region IO, again making partition regions more general.

Next Week

 

    I am a bit behind where I hoped to be on my schedule so far, as I have minimal work on generating overlay devices; however, my plan is to have partition region IOs supported to the best of my ability so the ideas can be easily translated over to overlay devices without having to redo my work later on.  With that said, the goal is to quickly finish up heterogeneous synth IO tiles next week and finally fully move onto overlay device generation.