June 12th, 2020 Progress Report

Progress

   After this week I have gained a much better understanding of how to approach the problem of partial reconfiguration.  My approach will diverge quite a bit from what I originally planned on, based on advice from litghost.  I also familiarized myself much more with the symbiflow-arch-defs cmake and begun creating a setup to support the partial reconfiguration regions discussed.  I also think this approach to partial reconfiguration closes the cap between offline and online pr.

Approach

   Each of the partial reconfiguration regions plus the overlay will be a different symbiflow-arch-defs device (they could potentially be combined in some way in the future to be considered sub-devices of a single full device).  Each partial reconfiguration region will be restricted in a very similar fashion to the ROI based on information in the design.json, or other similar file.  The overlay device will be the reverse, containing the entire chip but the partition regions.  We will make the constraint that partition pins must cross the partition region boundary to ensure proper isolation between regions and the overlay.  These partition pins will initially be decided manually, but they could in theory be optimized for routability.

First test partition region on the a50t, outlined by the black box: PR Region

     

    Synth IO tiles will be placed right outside of the partition region for each device, connecting to

the partition pins right on the other side of the partition region boundary.  The overlay will be treated in the opposite fashion, with synth IOs being placed inside what would be the partition region and connected right outside of the region.

    The overlay and partition region can then be placed and routed separately with VPR.  As a last combination step, the FASM of all the partition regions and overlay can be cated together to produce final FASM to generate a bitstream from.

Next Week

    Next week I will start with finishing a reasonable cmake configuration to make building easier, and then get into implementing the partition region device in the prjxray scripts.  This step will also include choosing reasonable partition pins and adding good synth IO tiles.  Depending on how that goes, the next step would be implementing graph exclusion to create a device that does not contain any of the partition region information.